<> Pecaution : * The Fast User Switching feature of Windows XP is not supported. Therefore, please do not use Rte for WIN32 by two or more users simultaneously. * Vr4181A-TP : The base address which sfr command uses is 0xbfa00000. It cannot be changed. * When Rte for WIN32 earlier than Ver5.03 is already installed, please once uninstall Rte for WIN32 of an old version and install Ver5.03 or later. It is better to uninstall, after you made a note of a setup of an address of ISA interface, the IP address of LANBOX, etc. 8.01.00 2012/09/24 < New Support > * Supports the E2N3-SPL(MultiCore). The license is required for E2N3-SPL. * Supports the G3M-SPL. The license is required for E2N3-SPL. < New function / change > * V850E2/MN4-TP : The sfr command was modified into the contents based on the V1.13a device file. * V850E2/ML4-TP : The sfr command was modified into the contents based on the V1.13a device file. * V850E2R/0134-TP/GT : ES4.0 CPU was supported. 8.00.00 2011/06/06 < New Support > * Supports Windows 7. Refer to RTE for WIN32 installation Manual Rev.7.0 or later. * Supports the V850E2/ML4-TP. The license is required for V850E2/ML4-TP. * Supports the E2N3-SPL. The license is required for E2N3-SPL. < New function / change > * V850E2/MN4-TP : The sfr command was modified into the contents based on the V1.10a device file. 7.05.00 2010/06/24 < New Support > * Supports the V850E2/MN4-TP. The license is required for V850E2/MN4-TP. * Supports the V850E2R/0134-GT(SingleCore) and V850E2R/0134 -GT(SingleCore/SlaveMode). < New function / change > * GigaTrace Function of V850E/3410-GT(IE,NWire) and V850E/ 3410-GT(TP,NWire) : The following function was modified. 1)4GByre memory was supported. 2)Sample timing of trace data was modified. 3)The Low drive of the TRCCE signal is always performed. * V850E2R/0134-TP : The trace parameter was added to the etkenv command. So, it can set up so that trace may be used on the ICE side in SlaveMode. * SlaveMode of V850E2R/0134-TP : Only an internal ROM area is possible for refer to the memory during run. The other area becomes an error. And, the data of the range which rte4w32 has not cached returns 0xff. * EP3-TP : CPU-ID returned to a Multi debugger was modified to V850E2V3 from V850E2R. Please use with the V5.1.7 or later Multi debugger. * Disassembler of V850E2R family : The instruction of the 850E2V3 architecture class3 was supported (support the following instructions). LD.B/BU/H/HU/W format XIV ST.B/H/W format XIV * V850E2R/0134-TP ,EP3-TP : The hardware break point function was modified as follows. - The break point of a ROM area : V850E2R/0134 : Only in an internal ROM area, the software break point by TuningRAM is used. EP3 : In all ROM areas, the software break point by EXTBRK function is used. - The BPH command is no longer supported. - The "exec" status conditions of the ABPn command is no longer supported. - The sequential conditions of the ABP command are no longer supported. - Setting of break point to the ROM area on MULTI debugger : V850E2R/0134 : At least 30-points break point assigning by TuningRAM is possible. ROM areas other than an internal ROM area cannot assign a break point. EP3 : To all ROM areas, 8 points break point assigning by EXTBRK function is possible. < Fixed problem > * Disassembler of V850E2R/0134-TP : The two following points were modified. 1)System registers other than bank common are displayed by sr0-sr27. 2)The displacement of sld.b, sst.b, sld.w, and sst.w instructions. * Disassembler of V850E2/ME3, NA85E2 and V850E2R/0134 : The least significant bit of the displacement of a ld.bu instruction is displayed incorrectly. * Disassembler of V850E/E1/E2/E2R family : The two following points were modified. 1)16bit/23bit displacement is displayed after signed extension. 2)The not1 instruction and the clr1 instruction are displayed conversely. * V850E2R/0134-TP/GP : When set up the synchronous break function effectively, The step execution will make other cores take a break. 7.04.00 2009/12/24 < New Support > * Supports the EP3-TP. The license is required for EP3-TP. * Supports the V850E/Ix4-TP. The license is required for V850E/Ix4-TP. < Fixed problem > * V850E/Ix4-TP ,V850E/MA3-TP ,V850E/PH3-TP ,V850E/Pxxx-TP , V850E/3444-TP ,V850E/3137-TP ,V850E/3410-TP ,V850E/3429-TP , V850ES/SJ2-TP ,V850E/3410-IE ,V850E/3429-IE : When Software BP sets to both an internal ROM area and the other area,BP of an internal ROM area cannot set up normally. * V850E2R/0134-TP ,HB001-SPL ,HB002-SPL ,PMN001-SPL ,UC001-SPL : When connection of JTAG becomes an error by the 1st time, It cannot connect as the RESET output became active after it. * V850E2R/0134-TP ,HB001-SPL ,HB002-SPL ,PMN001-SPL ,UC001-SPL : When a JTAG clock is relatively high to a CPU clock, the writing to memory sometimes cannot be performed normally. * V850E1/E2 family : The display of a disassembler, the jmp destination address of the relativity jmp by 16Bit displacement was not displayed correctly. * NB85E/V850E1/V850E2/V850E2R/V850E2M family : The address to which Software BP is set, and its address of +1 cannot be correctly read with 1Byte length in 1Byte access size. * UHS-Nwire Cable ,UHS-ETM Cable ,V850E2R/0134-TP : When trace is displayed, a time tag is not displayed near the end of a trace buffer. * V850E/3429-TP : The register displayed by sfr/sfr2 command is a register of V850E/3410. 7.02.04 2008/03/06 < Fixed problem > * V850E2R/0134-TP ,PMN001-SPL : In trace analysis, relativity JMP did not analyze correctly in some cases. In the disassembler display, the source and destination of an operand of a sst.w instruction were displayed conversely. 7.02.03 2009/02/26 < Fixed problem > * V850E2R/0134-TP ,PMN001-SPL : Reference/modification of the register of a MPU bank and the violation bank of MPU did not function correctly. This problem had occurred with Ver.7.01.Beta19 or later / Ver7.01.00 or later. * Vr4155-TP : When the status register of CP0 was modified from a debugger, FR bit of status register was always set to 0. 7.02.02 2009/02/04 < New Support > * V850E2R/0134-TP : ES3.0 CPU was supported. 7.02.01 2009/01/29 < Fixed problem > * PMN001-SPL : The instruction buffer was not supported. 7.02.00 2009/01/23 < Fixed problem > * RTE-2000H-TP : The execution control ,a register accessing function, etc. becomes sometimes unstable when using with PB-JTAG-N-A36 or PB-NEXUS-N50. * V850E2R/0134-TP ,PMN001-SPL : When a user program stops by a software break point, in the display of a trace result, the instruction of a break point was always displayed as NOP. 7.01.00 2008/12/23 < New Product > The following products which were being supported by the beta version were supported officially. * V850E2R/0134-TP The license is required for V850E2R/0134-TP. When using only ICE, select V850E2R/0134-TP(MultiCore). When using ICE with external RAM monitor tool, select V850E2R/0134-TP(MltiCore/SlaveMode). * PMN001-SPL The license is required for PMN001-SPL. < Fixed problem > * RTE-2000-TP : When a "OK" button is clicked on Check RTE2, The error "RTE-2000H SROM wasn't wrote." occurs rarely. * V850E/PG2-IE ,V850E/PS2-IE ,V850E/CS1-IE ,V850E/CW1-IE , Phoenix_F-IE ,V850E/MA3-IE : When a trace cache was enabled, fill to the internal ROM area did not work correctly. Memory is not updated although only a cache is updated. 7.00.00 2007/08/20 < New Product and Support > * Supports Windows Vista. Refer to RTE for WIN32 installation Manual Rev.6.0 or later. * Supports the Vr4155-TP (Preliminary release). The license is required for Vr4155-TP. < Fixed problem > * Vr4122-TP ,Vr4131-TP ,Vr4133-TP ,Vr4181-TP : The tlb command did not modify correctly the contents of TLB to which the INDEX register indicates. * NA85E2-TP ,V850E2/ME3-TP : When the following function was used, it did not take a break as expected. >> Run until the cursor line >> Return from current function 6.01.01 2007/05/07 < New function / change > * Supports NECEL debugger ID850QB Ver.3.40. 6.01.00 2007/02/08 < New Product and Support > * Supports the V850E/Pxxx-TP. The license is required for V850E/Pxxx-TP. * Supports the V850E/Pxxx-NBD. The license is required for V850E/Pxxx-NBD. * Supports the V850E/3444-TP. The license is required for V850E/3444-TP. < New function / change > * In some products, NECEL debugger ID850QB was supported. * V850E/PG2-IE : The sfr/sfr2 command was modified into the contents based on the V1.00 device file. * V850E/MA3-TP : The initial value of CPU input frequency for writing of internal FlashROM was modified to 8MHz from 20MHz. * V850E/PS2-NBD ,V850E/PG2-NBD ,V850E/GP1-NBD ,V850E/xxx-NBD : The SFR area can set as a RAM monitor area. * ARM Series -TP ,V850E/xxx-TP ,NA85E2-TP ,V850E2/ME3-TP : Add the size parameter(*1) to tenv command. * NB85E-TP ,NU85E-TP ,V850E/ME2-TP ,AS85EP2-TP ,Vr5432-TP ,Vr5500-TP , 　Vr7701-TP : Add the size parameter(*1) to tron command. *1:When RTE-2000H-TP is used, the size parameter sets up the trace buffer capacity to be used. < Fixed problem > * AS85EP2-TP : After accessing the internal instruction RAM with length 0 and accessing other memory area, read/write mode of the internal instruction RAM did not return to a user's mode. * ARM Series -TP : The tenv command did not display a setup of pack1/3. 6.00.02 2006/03/02 < Fixed problem > * The undefined error was displayed when a license error occurred. * The timing of the JTAG circuit of a UHS-NWIRE/ETM cable has been improved. 6.00.01 2006/01/26 < Fixed problem > * The license error had occurred with some IDs(MACID). 6.00.00 2006/01/23 < New Product and Support > * RTE-2000H-TP was supported with the following product. AS85EP2-TP, NA85E2-TP, NB85E-TP, NU85E-TP, V850E/3137-TP, V850E/3410-TP, V850E/3429-TP, V850E/MA3-TP, V850E/ME2-TP, V850E/PH3-TP, V850E/xxx-TP, V850E2/ME3-TP, V850ES/SJ2-TP, VR5432-TP, VR5464-TP, VR5500-TP, VR7701-TP, ARM922T-TP, ARM926EJS-TP, ARM946ES-TP, MP211-TP, OMAP_ARM-TP, OMAP161x_ARM-TP, ARM1136JFS-TP, OMAP24xx_ARM11-TP V850E/063-IE, V850E/065-IE, V850E/3410-IE, V850E/3429-IE, V850E/MA3-IE, V850E/PG2-IE A proper license is required to use -TP family with RTE-2000H-TP. The tdata_dly command was added for RTE-2000H-TP support. And, the format of the jtag clock frequency setting parameter of the env command was modified. * Supports the V850ES/SJ2-TP. The license is required for V850ES/SJ2-TP. * Supports the V850E/PH3-TP. The license is required for V850E/PH3-TP. * Supports the V850E/GP8-IE. * Supports the V850E/3448-IE. * Supports the V850E/PH3-NBD. The license is required for V850E/PH3-NBD. < New function / change > * V850E/MA3-IE,V850E/3410-IE,V850E/3429-IE,NA85E2-TP,V850E2/ME3-TP : The stpenv command is added. * NA85E2-TP : E2SS-Core was supported. * V850E/MA3-TP : The default of ifromenv command write parameter was modified to "Enable Auto Write" from "Disable Auto Write". < Fixed problem > * In the following products, After single step of the "DI" instruction, Interrupt was not disable (PSW register). V850E/MA3-TP ,V850E/MA3-IE ,V850E/3410-IE ,V850E/3410-TP , V850E/3429-IE ,V850E/3429-TP ,NA85E2-TP ,V850E2/ME3-TP , NB85E-TP ,NU85E-TP ,V850E/ME2-TP ,AS85EP2-TP , V850E/xxx-TP ,Phoenix_F-IE ,V850E/063-IE ,V850E/065-IE , V850E/PG2-IE ,V850E/GP1-IE ,V850E/GP2-IE ,V850E/xxx-IE , V850E/yyy-IE ,V850E/zzz-IE 5.13.00 2005/05/20 < New Product and Support > * Supports the V850E2/ME3-CB. * Supports the V850E2/ME3-TP. The license is required for V850E2/ME3 -TP. * Supports the V850E/3429-IE. * Supports the V850E/3429-TP. The license is required for V850E/3429 -TP. * Supports the V850E/3429-NBD. The license is required for V850E/3429 -NBD. * Supports the MP211-TP. The license is required for MP211-TP. * Supports the ARM926EJS-TP. The license is required for ARM926EJS -TP. * Supports the ARM1136JFS-TP. The license is required for ARM1136JFS -TP. * Supports the OMAP24xx_ARM11-TP. The license is required for OMAP24xx_ARM11-TP. * ARM9/11 Series -TP : Supports the BIF-D03. < New function / change > * V850E/3410-IE/TP : The time command was added. * V850E/3410-IE/TP : Supports the ES2.0/ES3.0 CPU. * V850E/3410-TP : Supports the Mass production CPU. * V850E/3410-NBD : The tblock command was added. * V850E/3410-NBD : Supports the ES2.0 CPU. * V850E/PG2-IE : The sfr command was modified into the contents based on the V1.00e device file. * V850E/PG2-IE ,V850E/063-IE ,V850E/065-IE : The accenv command was added. * V850E/065-IE : The sfr/sfr2 command was modified into the contents based on the V1.00d device file. * Vr5500-TP : The tclkdiv parameter was added to the env command. The tclkdiv parameters other than tclkdiv1 are available only at Vr5500A. * ARM9 Series -TP : Working speed via JTAG has been improved. For example, the download to a user memory became high speed about twice. The upload from a user memory became high speed about 3 times. * ARM9 Series -TP : After temporary power cut of JTAG, It takes a break normally. * ARM9 Series -TP : The brkrq parameter was added to the armopt command. * ARM926EJS-TP,OMAP161x_ARM9-TP,MP211-TP : The CP15 registers reference / change function of a GHS Multi debugger is supported. * ARM9/11 Series -TP : The init/reset sequence was modified. So In CPU which run at reset like ARM926,the time of run became short. * ARM11 Series -TP : The hsdownload command was added. * OMAP24xx_ARM11-TP : The keepclock/keeppower parameter was added to the armopt command. < Fixed problem > * V850E/xxx-NBD ,V850E/3410-NBD : "tcopy /all" had copied only the address range to 0x0-0xffff. 5.12.01 2004/07/26 < New Product and Support > * Supports the V850E/PG2-IE. * Supports the V850E/PG2-NBD. * Supports the AS85EP2-TP. The license is required for AS85EP2-TP. < New function / change > * ARM9 Series -TP : Supports the HiSpeed-ETM Cable. < Fixed problem > * ARM9 Series -TP (exclude OMAP_ARM-TP) : The user program does not run correctly, when it is used simultaneously with access break point and software break point. * ARM9 Series -TP : If resetrecovery of armopt command is set enable, The emulation memory cannot be accessed after occurrence or SRST-. * ARM922T-TP : Unnecessary cycle is displayed on the trace result before a break. 5.11.01 2004/01/27 < Fixed problem > * ARM9 Series -TP : The EMEM allocation of BID-Dxx board is modified by issue of a reset command. 5.11.00 2004/01/10 < Caution > * When LAN-I/F is used, the Rte4w32 Ver.5.11 or later must be used with the Partner debbuger Ver.3.30 or later. < New Product and Support > * Supports the LAN/USB I/F of RTE-2000-TP. * Supports the V850E/xxx-TP. The license is required for V850E/xxx-TP. * Supports the OMAP161x_ARM9-TP. The license is required for OMAP161x_ARM9-TP. * Supports the Phoenix_F-IE. * Supports the BIF-Dxx Adapter Board. < New function / change > * ARM9 Series -TP : Only ARM946ES-TP and OMAP161x_ARM9-TP can enable RTCK with the DIPSW1-4 of RTE-2000-TP. The other ARM9 series -TP, RTCK is always disable. The armopt command is added as part of OMAP161x_ARM9 support. * NA85E2-TP : New parameters (iqueue,dc_size,dc_way) for env command are added. The following command parameters and commands with use limitation was deleted. command | deleted parameter -----------+--------------------- abp | and env | nmi2 sswon/off | td{1..8} ,evep ,ever tron | td{1..8} td{1..8} | command itself * -TP Series : The allocation specification of the rom command was modified. Since there is upward compatibility of the previous specification, there is no necessity for change of a setup. * V850E/MA3-IE/TP : When accessing internal ROM space during break, the WAIT pin is masked. < Fixed problem > * V850E/MA3-IE ,NA85E2-TP : JMP-Self instruction could not trace correctly. * Vr4131-TP ,Vr4181A-TP ,Vr4133-TP ,Vr5432-TP ,Vr5500-TP , MIPS32_4Kc-TP : When all the following conditions are match, the writing of FlashROM is not correctly. * The cpu mode is big endian. * FlashROM type is AMD. * The width of data bus is 8-bit or 16-bit. * NB85E-TP ,NU85E-TP ,V850E/ME2-TP ,Vr5500-TP ,ARM946ES-TP , OMAP_ARM-TP ,ARM922T-TP : In delay mode ,Bustrace is not displayed. 5.10.02 2003/06/12 < New function > * NA85E2-TP : The writeback cache were supported. < Fixed problem > * V850E/MA3-IE : It was fixed about the DMAAK signal. 5.10.01 2003/06/06 < Fixed problem > * V850E/MA3-IE : A DMA transfer complete interrupt did not occur proper. 5.10.00 2003/06/04 < New Product and Support > * Supports the ARM922T-TP. * Vr5500-TP : Supports the Vr5500A. * Vr4133-TP : Supports the Rev1.2 CPU. < New function / change > * V850E/MA3-TP : The break point function using the ROM collection function was added. So, the break point which can be set up to an internal ROM area increased to a maximum of six points. The ifromfreq/ifromwrite/ifromverify commands were added for internal FlashROM writing support. * NB85E-TP,NU85E-TP,V850E/ME2-TP : The eva/eve/evt/seq commads were added. * V850E/ME2-TP : The sfr command was modified into the contents based on the V1.10 device file. The default of reset mask (env command) was modified into mask from not mask. * Vr4133-TP : The sfr command was modified. * Vr5432-TP,Vr5500-TP,Vr4122-TP,Vr4131-TP,Vr4133-TP,Vr4181A-TP : Support of the flash ROM of an Intel family was added. * OMAP_ARM-TP : The work_addr command was added. * ARM946ES-TP : The software Break point code was changed. So even if Software BP was used in both the modes of ARM/Thumb, one Hardware BP could be used. * ARM946ES-TP,OMAP_ARM-TP : Even if Software BP was used, the Access BP could be used. Hardware BP and Access BP can be used simultaneously. < Fixed problem > * V850E/MA3-IE,NA85E2-TP : The time tag information in relative time format on data trace was not displayed proper. * NB85E-TP,NU85E-TP,V850E/ME2-TP,V850E/GP1/2-IE,V850E/xxx-IE,V850E/yyy -IE,V850E/zzz-IE,V850E/MA3-IE : Some cases the abp with exec parameter does not function proper. * V850E/GP1/2-IE,V850E/xxx-IE,V850E/yyy-IE,V850E/zzz-IE : When abp was set at the internal ROM area, the mask conditions of address did not function proper. * Vr4122-TP,Vr4131-TP,Vr4133-TP,Vr4181A-TP : When 64Bit mode was set with the RTE-1000-TP ,an error "Can not find RCP file" had occurred. * ARM946ES-TP,OMAP_ARM-TP : The single step of the instruction which transmits the contents of a cpsr register and other registers did not function proper. * OMAP_ARM-TP : The software BP at 4n+0 address in Thumb mode did not function proper. * OMAP_ARM-TP : Some cases the contents of a display of data trace were not proper. It modified so that it might be displayed more proper. * Intel family Flash ROM Support : When the cpu bus width was wider than the bus width of the ROM, it was not able to write in proper. 5.09.01 2003/03/18 < Fixed problem > * RTE-2000-TP : The rom command with bus width 32Bits or 64Bits does not function correctly. < V850E/MA3-IE/TP > * Some registers for sfr command were deleted. 5.09.00 2003/03/11 < New Product > * Supports the V850E/MA3-IE. * Supports the V850E/ME2-CB. * Supports the Vr4133-TP(preliminary support). The license is required for Vr4133-TP. * Supports the E2DP1-NBD. < New function > * NA85E2-TP : Supports the High Speed N-Wire Cable (RTE-NEC/MICTOR38 -2K-2). * V850E/ME2-TP : Supports the High Speed N-Wire Cable (RTE-NEC/MICTOR 38-2K-2). * ARM946ES-TP ,OMAP_ARM-TP : Supports the string command for ETM. * Vr4131-TP : Supports the ES2.2 CPU. < Fixed problem > * NA85E2-TP : The display of td1 - td8 command was not correct. * ARM946ES-TP ,OMAP_ARM-TP : The writing of FlashROM of AMD family series does not function correctly. * RTE-2000-TP : The nrom command does not function correctly. * RTE-2000-TP with Partner Debugger : When displaying the BusTrace, the display of trace locked. 5.08.00 2002/11/20 < Fixed problem > * ARM946ES-TP ,OMAP_ARM-TP : With Green Hills Software's Multi Debbuger, the contents of cpsr ,r8_usr - u14_usr registers are not displayed correctly. * NB85E-TP ,NU85E-TP ,V850E/xxx-IE ,NA85E2-TP ,V850E/MA3-TP : By the case, the single step of reti instruction does not operate correctly. 5.07.00 2002/11/18 < New Product > * Supports the V850E/ME2-TP. The license is required for V850E/ME2-TP. The read/write operation from the debugger to an internal instruction RAM address area are performed to internal instruction RAM. This is not dependent on a setup of internal instruction RAM mode. It cannot Run, when the value of PC register points internal instruction RAM area, and internal instruction RAM is set write mode. * Supports the NA85E2-TP. The license is required for NA85E2-TP. * Supports the V850E/MA3-TP. The license is required for V850E/MA3-TP. The "option" button was added to ChkRte2. * Supports the Vr7701-TP. The license is required for Vr7701-TP. * Supports the OMAP_ARM-TP. The license is required for OMAP_ARM-TP. * Supports the V850E/GP1-IE and V850E/GP2-IE. * Supports the V850E/GP1-NBD. The license is required for V850E/GP1-NBD. * Vr series -TP : Supports 64Bit register mode. With Green Hills Software's Multi Debbuger, when you use 64Bit registers, please set up 64Bit mode. < New function > * Supports the Green Hills Software's Multi2000 (Multi Rel6). Please use Multi of Rel6.5.2a with point release pr0805 and pr0809, or later. * NB85E-TP ,NU85E-TP : Supports the Intel Flash ROM. < Change > * Vr5500-TP : CPUID for the Green Hills Software's Multi was changed to Vr5500 from Vr5400. * Vr4122-TP ,Vr4131-TP ,Vr4181A-TP : Without changing LCR register bit 7, the sfr command can reference/change the UART registers. < Fixed problem > * Vr4131-TP : The sfr command does not operate correctly in big endian mode. * Vr4122-TP ,Vr4131-TP : By the case, the sfr command were deadlock. * Vr series -TP ,MIPS32_4Kc-TP : By the case, the contents of CONFIG register are not maintained correctly. * Vr series -TP : The ind/outd command cannnot use. 5.06.00 May. 02, 2002 < New Product > * Supports the NU85E-TP. The license is required for NB85E-TP. * Supports the V850ES/SA3-CB. * Supports the V850E/yyy-IE and V850E/zzz-IE. * Supports the V850E/IA1-NP. This product is for connecting with "Starter Kit V850E/IA1" which NEC has released. * V831/2-TP and MIPS32_4Kc-TP supports the RTE-2000-TP. < New > * Vr4131-TP : Supports the ES2.2 CPU. * RTE-NBD2 : Add the Real-time transmission feature. * ARM946ES-TP : Supports the Intel Flash ROM or compatible. < -TP Series > * NB85E-TP ,Vr5500-TP ,ARM946ES-TP : Supports the external bus trace feature of RTE-2000-TP. * ARM946ES-TP : The memory 32bits read/write got fast (about 4 times prior). 5.05.00 Jan. 19, 2002 < New Product > * Supports the Vr5500-CB. * Supports the Vr5500-TP. The license is required for Vr5500-TP. * Supports the MIPS32_4Kc-TP (preliminary support). The license is required for MIPS32_4Kc-TP. * Supports the Vr4131-TP. The license is required for Vr4131-TP. * Supports the Vr4181A-TP. The license is required for Vr4181A-TP. * Supports the V850ES/SA3-CB (preliminary support). * Supports the ARM946ES-TP. The license is required for ARM946ES-TP. < New > * Windows XP Professional and Windows XP Home Edition are supported. The Fast User Switching feature is not supported. Therefore, please do not use Rte for WIN32 by two or more users simultaneously. * Supports the RTE-2000-TP. The product which can be used by RTE-2000 -TP is as follows. Vr5432-TP,Vr5500-TP,Vr4122-TP,Vr4131-TP,Vr4181A-TP,NB85E-TP, ARM946ES-TP < V850-IE Series > * In the contents displayed by map command, the error was in the length of the block before internal area. This problem has been fixed. < V850E-IE Series > * The exec was upgraded from E5.41b to E5.60c. And, even when the target was not connected, target attribute could be assigned by map command. < V850E/IA1-IE > * The device file was changed to V1.21. Some registers for sfr command were changed to read only. Some register names for sfr2 command were modified. < V850E/xxx-IE > * Some registers for sfr/sfr2 command were added or deleted. The address of M_DATA010 register was modified in sfr2 command. < -TP Series > * NB85E-TP,Vr4122-TP,Vr5500-TP,ARM946ES-TP : In the cash area of ROM, software breakpoint did not operate correctly. This problem has been fixed. < Vr4122-TP > * The cacheinit command was not functioning correctly. This problem has been fixed. 5.04.00 May 26, 2001 < Vr5432-TP > * It modified so that the frequency of the JTAG clock which can operate might be searched for at the time of initialization. The JTAG clock is tried sequentially from high frequency(25MHz). Therefore, with some target, the frequency of JTAG clock at the time of starting change from 12.5MHz to 25MHz. * When the area to which Ready does not return was accessed, the deadlock had occurred. This problem has been fixed. < Vr4122-TP > * Supports the ES3.1 CPU. * It modified so that the frequency of the JTAG clock which can operate might be searched for at the time of initialization. The JTAG clock is tried sequentially from high frequency(25MHz). Therefore, with some target, the frequency of JTAG clock at the time of starting change from 12.5MHz to 25MHz. < Mips Series -TP > * When RTE-1000-TP was used, every time it issued rom command, the toggle of the endian of rom had occurred. This problem has been fixed. < V850E/xxx-IE > * The time command (run time measurement feature) is added. * When No. 7 of DIP-SW was set as OFF, RTE-NBD2 linked to ICE had caused the timeout error in ChkRte. This problem has been fixed. < V850E-IE , V850-IE Series > * V850E/PS1-IE : sfr2 command is added. And, a part of register of sfr command was deleted. * V850/SA1-IE : Some of register name of sfr command was modified. 5.03.00 Dec. 22, 2000 < New Product > * Supports the V850E/PS1-IE (preliminary support). * Supports the V850E/PS1-NBD. The license is required for V850E/PS1- NBD. * Supports the V850E/xxx-IE. * Supports the V850E/xxx-NBD. The license is required for V850E/xxx- NBD. * Supports the V850E-SIM(V850E/xxx). The license is required for V850E-SIM(V850E/xxx). < NB85E-TP > * It modified so that the frequency of the JTAG clock which can operate might be searched for at the time of initialization. The JTAG clock is tried sequentially from high frequency(25MHz). Therefore, with some target, the frequency of JTAG clock at the time of starting change from 12.5MHz to 25MHz. < Vr4122-TP > * The CPU of ES2.1 and ES3.0 was supported. "VR4122-TP (32Bit)" supports the CPU newer than ES3.0. There is no limitation (preliminary support). "VR4122-TP (32Bit-ES3.0)" supports the CPU after ES3.0. The trace clock of the CPU is used for the JTAG clock. Do not modify a setup of a trace clock by env command. "VR4122-TP (32Bit-ES2.1)" supports the CPU of ES2.1 and ES3.0. Since it is for specific users, there are very many limitation. Normally, do not use this. < V850E-IE Series > * V850E/MA1-IE/-CB : Some of register names of sfr command was modified. * V850E/IA1-IE : Some of register names of sfr/sfr2 command was modified. The emulation memory for external bus has not been accessed. This problem has been fixed. < V850-IE Series > * V850/SB1-IE : The item chosen on ChkRte was made for every built-in ROM / RAM capacity. The selection item "V850/SB1-IE" was deleted. * V850/SBx-IE : Supports the V850/SB2. The register for V850/SB2 was added to SFR command. < The other > * Vr5432-TP and Vr4122-TP : When used with LAN-BOX, it might not operate normally. This problem has been fixed. 5.02.00 Aug. 17, 2000 < Vr5432-TP > * When 1000-TP was used, the speed of download / upload / fillup to/from the user memory became fast 5.8 - 6.3 times (PCI-I/F Card). * The speed of download / upload to/from the emulation memory became fast about 2.8 times (PCI-I/F Card). * In the display of a trace result, the analysis of EXP packet was wrong. This problem has been fixed. * Only when the user changes the value of the Compare Register during break, the value is set to the Compare Register. < NB85E-TP > * When 1000-TP was used, the speed of download / upload to/from the user memory became fast 1.5 - 4.3 times (PCI-I/F Card). * The speed of download / upload to/from the emulation memory became fast about 2.8 times (PCI-I/F Card). * The mask of RESETZ, STOPZ, and HOLD (VAREQ) signal was not functioning normally. This problem has been fixed. < V831/2-TP > * When 1000-TP was used, the speed of download / upload to/from the user memory became fast 1.6 - 2.7 times (PCI-I/F Card). * The speed of download / upload to/from the emulation memory became fast about 2.8 times (PCI-I/F Card). < V850E/IA1-IE > * sfr2 command was added. < The other > * When using the personal computer which has two or more PCI buses, the PCI card has not been recognized on Windows NT4. This problem has been fixed. * On Windows NT4, if "Card Executive 2.0 for NT" was installed, the PC-Card interface has not been recognized. This problem has been fixed. * With the Partner debugger, a memory fill command bigger than 64K bytes did not function normally. This problem has been fixed. 5.01.00 May. 05, 2000 * V850E/IA1-IE : The product which supported hardware Rev.1.0 was changed to "V850E/IA1-IE (Old_Type)", and the product which supported Rev.2.0 or later was added as "V850E/IA1-IE." * Supports the Vr4120-TP (preliminary support). The license is required for Vr4120-TP. * NB85E-TP : In the case of CPU which does not build in the trace unit, ChkRte had caused the error. This problem has been fixed. 5.00.00 Apr. 16, 2000 < License > * V30MZ-TP, V831/2-TP, Vr5432-TP, NB85E-TP, and V850E/IA1-NBD : When these products are used, a setup of the license by ChkRte2.exe is needed. In use of RTE-V831/2-TP (older model than RTE-100-TP), it can use without setting up a license, even if ChkRte2 is displayed "License is not available" when V831-TP or V832-TP is chosen. < New Product > * Supports the Windows2000. * V831/2-TP, NB85E-TP and Vr5432-TP : Supports the RTE-1000-TP. < V831/2-TP, NB85E-TP, Vr5432-TP > * When the Partner Debbuger is used, the write function to FlashROM is supported. * NSBP, NSBPD, NROM, and NROMD command are added. < NB85E-TP > * In 256M byte mode, when a break was taken, there was a case where a redundant memory read cycle occurred. This problem has been fixed. * There was a case where a single step did not operate normally. This problem has been fixed. * When a break was taken, the contents of data cache was not write back, but they were cleared. This problem has been fixed. * When a break was taken, the value of DCC register was cleared. This problem has been fixed. The contents of a cache tag are also cleared when the data cache are flashed. The cache tag were not cleared in an old version. < V850E-IE Series > * The r3(sp) register is initialized at the time of starting and reset. * The end of the trace caused in Run is not notified. In the combination with the Partner debbger, there was a case where the trace-on issued in Run did not function normally. These problems have been fixed. < V832-TP > * If the CPU Halts during trace, the CPU may deadlock very rarely. In this case, a force break can be issued. 4.37.00 Dec 16, 1999 < New Product > * Supports the V850E/MA1-IE. * Supports the V850E/IA1-NBD. < NB85E-TP > * The trace display of instruction over 6 bytes was not correct. This problem has been fixed. * In some cases, Single step did not function properly. This problem has been fixed. * At break time, the content of data cache was flashed without writeback. This problem has been fixed. * When the content of data cache was flashed, tag was not cleared. This problem has been fixed. * At break time, the content of DCC register was cleared. This problem has been fixed. * The data trace display was not correct. This problem has been fixed. < -TP Series > * NB85E-TP,Vr5432-TP and V831/2-TP : The 32Mbit ROM became able to use with RTE-100-TP(8MByte). * Vr5432-TP : Hi-speed download mode has been added. * Vr5432-TP : The cacheinit command has been added. When uninitialized cache area is accessed, the cacheinit command must be issued previously. < The other > * -PC and -CB series of Mips CPU : The profile display of Multi debugger was not correct in big endian mode. This problem has been fixed. 4.36.00 Sep 17, 1999 < New Product > * Supports the Vr5432-CB. * Supports the Vr5432-TP by KIT-Vr5400-TP. The RTE-200-TP is required as a probe. * Supports the NB85E-TP by KIT-NB85E-TP. The RTE-100-TP is required as a probe. * Supports the V850E/IA1-IE. * Supports the V850/GW1-IE. * Supports the V833-PC. < Vr5464-TP > * Trace trigger could be not properly triggerd, but now, they can. < -TP Series > * In the V831/2-TP,Vr5464-TP and NB85E-TP, jread command could not properly work when the address is not aligned 4n+0, but now, the can. < Notes > * When using the Multi as a debugger with NB85E-TP/CB,V850E/IA1 -IE or other V850E Series, use the rteserv its version above the Rel.4.0.3. Ohterwise the register CTBP,CTPC and CTPSW are not display correctly. * If you use the Beta version of rte4w32, please uninstall beta version befor installing new version. 4.35.00 May 01, 1999 < New Product > * Supports the RTE-Vr5464-PC. When using the Multi as a debugger, use the version above the V1.8.9 Point Release 285(pr285). * Supports the RTE-V850E/MA1-CB. * Supports the RTE-NB85E-CB. * Supports the RTE-V830R/NV-CB. * Supports the RTE-V850/SB1-IE. * Supports the KIT-Vr5464-TP(32-bit)(tentative). The RTE-200-TP is required as a probe. When using the Multi as a debugger, use the version above the V1.8.9 Point Release 285 (pr285). * Supports the KIT-V830R/NV-TP(tentative). The RTE-100-TP is required as a probe. < RTE-PC Mips Series > * In the RTE-PC Mips series, the ioread and iowrite commands could not properly run when the CPU mode is Big, but now, they can. < RTE-PC V85x Series and V850E/MS1 > * In the RTE-V850-PC series and RTE-V850E/MS1-PC, the ioread and iowrite commands have been added. Those commands can control an access size at memory access. They are used when accessing memory mapped I/O. < RTE-IE V85x Series > * In the RTE-V850-IE series, the reverse assembly binary arrangement has been modified at trace display with the trace command of the rte4w32. * In the RTE-V850-IE series, the default value of the time command has been modified to an appropriate value for each probe. * In the RTE-V850-IE series, the ftimeout command has been added. The ftimeout command can control the monitor timeout time when filling the memory. Normally, use a default value as it is. When the CPU operating frequency is very low(lower than 1 MHz) with the CPU of the V850/SA1, and so on, set a value greater than the default value. The numeral set with ftimeout is the timeout time in seconds when filling 0x1000 bytes at 32-bit access. By default, it has been set to "0.6," which indicates that the timeout time of 0.6 second is applied to fill the 0x1000 bytes if an access size is 32 bits, and 2.4 seconds(0.6 x 4) if the access size is 8 bits. < RTE-TP V83x Series > * The RTE-V831/2-TP is now capable of accommodating the full trace mode (when using the command of the rte4w32, use the tron command to specify !real). If the full trace mode is enabled, the CPU internal tracing FIFO will not overflow and all the operating conditions of the program can be traced, but the program will not run at real time. This is because in the full trace mode, a break takes place just before the CPU internal FIFO becomes full, and the program automatically continues to run through software processing. Although it depends on the throughput of the personal computer, it runs 10 times or more slower than real-time run. A break for full trace takes place only when the trace data is being taken in. When trace is turned off or after the trace data has been taken in during the number of cycles specified in the delay mode, there will be no breaks occurring for full trace. * The RTE-V831/2-TP has the verify mode added to the env command. After the data is written into the memory, this function reads it out to verify whether it has been written successfully. At this time, in reading the memory used for the verify function, memory read by the CPU is always used even at the address where a relevant area has been emulated by the ROM. This function can be used to find an erroneous allocation of the Emulation ROM. By turning on the verify function in downloading to the ROM area, it can be found out that a verify error takes place and the Emulation ROM is not properly allocated, if the Emulation ROM has been erroneously allocated. * The RTE-V831/2-TP did not run the abpd command properly, but it does now. * The RTE-V831/2-TP could not delete abp properly, but it can now. * The RTE-V831/2-TP can now mask an interrupt at the time of single step operation. * The RTE-V831/2-TP does not single-step the HALT and STBY instructions any more. If they are single-stepped, an error will result. * If the RTE-V831/2-TP does not break at single step mode, it is now forced to break automatically. * In the RTE-V831/2-TP, if an error occurs at the time of single step operation, the hardware BP may result in an illegal state, but it has been modified. * In the RTE-V831/2-TP, the reverse assembly binary arrangement has been modified at trace display with the trace command of the rte4w32. * In the RTE-V832-TP, setting of the Internal Instruction RAM (to be referred to as IIRAM hereinafter) operating Work RAM has been added to the env command. When referring to/altering the IIRAM, it is necessary to set the Work RAM with the env command in advance. The V832-TP now requires the Work RAM when referring to/altering the contents of the IIRAM. The Work RAM requires 32 bytes and the Internal Data RAM cannot be specified. There are two setting methods; one is to specify an optional address ("env iaddr xxxx"), and the other one is to specify stack ("env istack"). Even if either method is selected, the memory data will not be destroyed because it restores the original memory data after the IIRAM is operated. If the IIRAM is included in downloading of the program, the Work RAM must be ready to read/write at the time of downloading. < RTE-IE/TP > * In the RTE-IE and RTE-TP series, the argument of exit() could not be properly transferred to the Multi, but it can be now. < In general > * A directory including half spaces was unavailable as an installation destination for "RTE for WIN32", but it is available now. * The maximum number of symbols readable with the symfile command has been altered from 8,150 to 32,760. * When reading with the symfile command, it now reads the data, omitting certain long symbol names generated by the Multi V1.8.9. In the Multi V1.8.9, unlike V1.8.8, certain symbols (static variables or functions) now include the absolute path names for the source file (actually, those converted from the absolute path names). This may greatly increase the number of symbol characters, depending on the compiling environment. In order to prevent such an excessive increase in the number of symbol characters, the rte4w32 now reads, omitting such symbols so that the symbols will be identical to those for V1.8.8.　 Specifically, a directory name is now eliminated from the absolute path name (directory name + file name) for the source file included in the symbol. Symbol for V1.8.9 -> _ChkAll..D.3A.5CV831.2EPC.5CCHKPR0.5Cchkpro. Symbol after conversion -> _ChkAll..chkpro. This makes only one of the symbols valid, if the source files with the same file name exist in different directories and those files contain the same static symbols. When you have to differentiate such two symbols from each other, alter the file name. 4.34.00 Dec. 3, 1998 * Special commands have been added to the RTE-V832-TP in order to accommodate the CPU of ES2.0 or ES2.1. * Supports the RTE-V853A-IE. 4.33.00 Oct. 16, 1998 * In the RTE-V83x-TP, timeout did not function properly at the time accessing the memory/I/O from the debugger, but it does now. 4.32.00 Aug. 27, 1998 * In the RTE-V85x-IDB/NBD, there was an error indicating that the ChkRTE32 was an illegal CPU when the CPU is of 160-pin type, but it has been modified. This error used to occur with Ver.4.24 or later. 4.31.00 Jul. 31, 1998 * The Windows98 has been added to the support operating system. The following three new problems with V4.30 have been modified. * With the NEC PC-9800, the ChkRTE32 did not display the PC-Card items. * With some units of the NEC PC-9800, a protection exception occurred if the ChkRTE32 was started. * With the NEC PC-9800, a default install directory for setup.exe did not assume the drive A:. 4.30.00 Jul. 17, 1998 * The installer (setup.exe) has been renewed. * The WindowsNT cannot install any more unless the Admin authority is given. * The WindowsNT4.0 for the PC/AT compatible machine (DOS/V machine) now supports the PC-Card interface. When using the PC-Card with the WindowsNT4.0, select an option to install a PC-Card driver at the time of installation. * A PC-Card address can be now acquired automatically with the Windows95. * The interface card name displayed with the Chkrte32 has been altered as follows: Old New ------------------------------------------------------------- "PC Card (I/O Port)" "PC Card" "Host Card (I/O Port)" "ISA I/F" 　(PC is PC/AT compatible） "C-BUS I/F"（PC is NEC98） "PCI Host Card" "PCI I/F" "TCP/IP" "LAN-BOX" * When used with LAN-BOX, the RTE-V850-IE series sometimes did not start due to an initialization error, but this has been modified. This issue had been found with Ver.4.24 and Ver.4.25. 4.25.00 Jun. 23, 1998 * The RTE-TP and RTE-IDB/NBD series did not operate in combination with the PCI-HOST card, but they do now. 4.24.00 Jun. 15, 1998 * Supports the RTE-V832-PC. * Supports the RTE-V832-TP. * Supports he host card for the PCI bus. * If the RTE-V831-TP continues to run, leaving an access break point valid after breaking with ABP (access break) or single-steps, it used to break without executing even one instruction, but it does not now any more. * The RTE-V831-TP sometimes made a mistake in analyzing a branch destination address in trace display, but it does not now. * The RTE-V830-PC accommodates the ROM versions, Ver.2.00 or above. * The RTE-V831-PC accommodates the ROM versions, Ver.2.00 or above. * The RTE-V850E/MS1-PC accommodates the ROM versions, Ver.2.00 or above. * Performance for downloading, etc. has been improved for the RTE-V850-IE series, RTE-V831-TP, RTE-V30MZ-TP, and RTE-V85x-IDB/NBD. 4.23.00 May 09, 1998 * In the RTE-V850-IE series, the address A[31:24] is now masked when caching the memory data. (When the stack pointer used PARTNER to debug the user program located in the address 0x1000000 or above, operations such as single step used to slow down) * When the CPU was ES4.0 of V85x in the RTE-V85x/IDB/NBD, the CPU was not recognized, but it is now. 4.22.00 Jan. 9, 1998 * In the RTE-V850E/MS1-PC, the RWC register has been added to the SFR command. 4.21.00 Jan. 6, 1998 * The RTE-V850E/MS1-PC sometimes could not successfully read/write the data with the SFR command when a data size was other than 8 bits, but it can now. * The RTE-V831-TP did not properly display execution of the TRAP instruction in trace display, but it does now. * The RTE-V831-TP displayed only the lower 8-bit bus data of the Trace command, but this has been modified. * If the RTE-V831-TP performs single step operation of the TRAP instruction, it used to break upon returning from exception processing, but it does not any more. 4.20.00 Dec. 15, 1997 * New API has been added for Green Hills Software's Multi. Since the Midas Server(rteserv), Release 3.0.2 or later, for the Multi uses this new API, it runs only on the RTE4W32, V.4.20 or later. * The RTE-V831-TP has been added. * The RTE-V30MZ-TP has been added. * The RTE-V850/SA1-1E has been added. * The RTE-V850E/MS1-PC has been added. * The RTE-Vr4310-PC has been added. * In the RTE-Vr4300-PC and RTE-Vr-4100-PC, the instructions and registers extended from the V4000 are now displayed on the Multi. * The RTE-PC series having the SFR, IOREAD, and IOWRITE commands sometimes could not read/write the data successfully with those commands when a data size was other than 8 bits, but it can now. * In the RTE-V85X-IDB/NBD, when the address A[24:31] other than 0 was specified in addressing of the fread/fwrite command or NBD-Manager, an error message, "Address value out of range," used to be displayed, but this has been modified. * In the RTE-V850-IE series, if the "help" command was executed in the TARGET window of the Midas Server (rteserv) for Green Hills Software's Multi, rteserv dropped due to page violation, but this has been modified. 4.15.00 Aug. 5, 1997 * In the RTE-V85X-IDB/NBD, when mismatch(!) was specified in setting the data of the ev[1/2] command, it was displayed match instead of mismatch in the screen, but this has been modified. Mismatch specification of the address condition and data condition did not function as a save parameter, but this has been modified. * The RTE-V85X-IDB/NBD sometimes displayed an error message, "Cannot Break," at break time, but this has been modified. 4.14.00 Jul. 7, 1997 * When the RTE-V85X-IDB/NBD checked NBD with CHKRTE, it used to doso, mapping the Tuning RAM accessible from the CPU, and therefore, the CPU sometimes crashed, but this has been modified. * If the RTE-V85X-IDB/NBD wrote into the Tuning RAM with the twrite command when the Tuning RAM was turned off with the tenv command, the subsequent fread command used to make the Tuning RAM visible, but this has been modified. * In the RTE-V85X-IDB/NBD, a tron command delay value was not saved and always amounted to 0x1ffff by default, but the previous input value is now saved. An initial delay value was modified to 0xffff. * In the RTE-V85X-IDB/NBD, a default value for data masking with the ev[1/2] command was 0x0, but modified to 0xffffffff. * In all the products where the sfr command is available, a space had to be secured before the register name and "=" with the sfr command's parameter, but now, no space is required any more. * In the RTE-V830-PC and RTE-V831-PC, the dctr, ictr, pllcr, and cmcr commands resulted in an error message, "Command not found," but this has been modified. 4.13.00 May 21, 1997 * In the RTE-V85X-IDB/NBD, the CPU sometimes did not output an event even if ev1 or ev2 was set, resulting in no occurrence of trace trigger or break by the event, but this has been modified. * In the RTE-V85X-IDB/NBD, no error was generated if the event(ev1 or ev2) not set with the tron command was specified in the recording cycle, and trace was not set either, but this has been modified. 4.12.00 May 15, 1997 * If a short(16-bit) or long(32-bit) size was specified with the ioread or iowrite command while the RTE-VR4300/4100-PC or RTE-VR5000-PC uses the CPU in the big-endian mode, the data was read/written, replacing its upper and lower bits with each other, but this has been modified. * In the RTE-V850-IE series, if Go execution was started from "stsr psw,rxx" or that instruction was single-stepped, the contents of the r2 or r5 register were destroyed, but this has been modified. * In the RTE-V85X-IDB/NBD, if timeout took place while scanning with the RAM monitor function, a scan number for the display data was shifted, but this has been modified.(NBD-Manager should be Ver.1.1 or above) * In the RTE-V85X-IDB/NBD, event output from the CPU was not prohibited if ev1 and ev2 were deleted, but it is now prohibited. 4.11.00 Apr. 10, 1997 * In the RTE-V85X-IDB/NBD, if NBD-Manager was brought up after starting srteserv of the Multi, an error message, "Can not control ICE," was sometimes displayed depending on operation on the Multi side, but this has been modified. 4.10.00 Mar. 18, 1997 * The RTE-V85X-IDB/NBD now runs on the Windows NT. * The file read with the symfile internal command has been changed from the .sym file output by the Multi to the ELF file. * The DC register was not available for the SFR command of the RTE-V831-PC, but this has been modified. * When the RTE-V85X-IDB/NBD selected words as an access size, a verify error occurred in downloading to the Flash ROM area, but this has been modified. * When the RTE-V85X-IDB/NBD displayed an error message, "Can not control ICE," it can be now cleared with "reset." * At the time of installation, an unfrozen file was apt to be installed with the date of unfreezing, but this has been modified. 4.00.00 Feb. 28, 1997 * Initial edition